The present invention relates to the fabrication of improved vertical metal oxide semiconductor field effect transistors (MOSFETs).
A MOSFET is used in forming dynamic random access memory (DRAM). A DRAM circuit usually will include an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bitlines. Typically, a DRAM memory cell comprises a MOSFET connected to a capacitor. The capacitor includes gate and diffusion regions which are referred to as either drain or source regions, depending on the operation of the transistor.
There are different types of MOSFETs. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is generally perpendicular to the primary surface of the substrate. A trench MOSFET is a transistor where a surface of the channel region of the transistor is not parallel to the primary surface of the substrate and the channel region lies within the substrate. For a trench MOSFET, the surface of the channel region is usually perpendicular to the primary surface, although this is not required.
Specifically, trench capacitors are frequently used with DRAM cells. A trench capacitor is a three-dimensional structure formed into a silicon substrate. This is normally formed by etching trenches of various dimensions into the silicon substrate. Trenches commonly have N+ doped polysilicon as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates, a dielectric layer is placed which thereby forms the capacitor.
To prevent carriers from traveling through the substrate between the adjacent devices, e.g. capacitors, device isolation regions are formed between adjacent semiconductor devices. Generally, device isolation regions take the form of thick field oxide regions extending below the surface of the semiconductor substrate. The most common early technique for forming a field oxide region is the local oxidation of silicon (xe2x80x9cLOCOSxe2x80x9d) technique. LOCOS field oxidation regions are formed by first depositing a layer of silicon nitride (xe2x80x9cnitridexe2x80x9d) on the substrate surface and then selectively etching a portion of the silicon nitride layer to form a mask exposing the substrate where the field oxidation will be formed. The masked substrate is placed in an oxidation environment and a thick silicon oxide layer is grown at the regions exposed by the mask, forming an oxide layer extending above and below the surface of the substrate. An alternative to LOCOS field oxidation is the use of shallow trench isolation (xe2x80x9cSTIxe2x80x9d). In STI, a sharply defined trench is formed in the semiconductor substrate by, for example, anisotropic etching. The trench is filled with oxide back to the surface of the substrate to provide a device isolation region. Trench isolation regions formed by STI have the advantages of providing device isolation across their entire lateral extent and of providing a more planar structure. Using improved isolation, continued reductions in size are possible.
DRAM technology for 1 Gb and beyond requires the use of vertical MOSFETs to overcome the scalability limitations of planar MOSFET DRAM access transistors. However, although vertical MOSFETs allow the bit densities required for effective size reduction, the use of vertical MOSFETs may result in performance and yield reduction tradeoffs.
For example, as the result of increased gate conductor to bitline diffusion overlap area, total bitline capacitance may be larger with vertical MOSFETs than with conventional planar MOSFET structures. Such a prior art structure is shown in FIG. 1 which is a cross-sectional view of a vertical MOSFET in which the vertical gate conductor 10 overlaps the entire depth of the bitline diffusion 20. Prior art attempts to address this concern generally require that the depth of the bitline diffusion be minimized. However, minimization of bitline diffusion depth is complicated by the fact that integration requirements may dictate a relatively high thermal budget (i.e., bitline diffusion (XA) needing to be performed relatively early in the process).
An additional concern encountered with vertical MOSFETs is the occurrence of diffusion stud (CB) to gate conductor (DT) shorts. These short circuits may result from misalignment between the edge of the wordline (WL) 16 and the edge of the deep trench 15, as shown in FIG. 2.
Yet another chronic problem with vertical MOSFETs is parasitic backside conduction. This issue arises as the distance between deep trench sidewalls is scaled below 100 nm. At this proximity, the adjacent wordline exerts an increasing influence on the potential in the silicon in the body of the vertical MOSFET. This influence increases the likelihood of leakage conduction between the storage node 22 and bitline diffusions 20, as illustrated in FIG. 3. When the adjacent wordline is high, it maybe possible to form a weakly inverted conductive path on the backside of the vertical MOSFET.
What is needed is a process for fabricating a scalable vertical MOSFET structure with minimized adverse performance and yield impacts.
Now, according to the present invention, an improved process for making a vertical MOSFET structure has been developed which features reduced gate to top diffusion overlap capacitance (reduced bitline capacitance), reduced bitline diffusion area, reduced incidence of diffusion to gate shorts (reduced incidence of CB-DT shorts), and improved immunity to backside parasitic conduction.
The improved vertical MOSFET structure is accomplished by a process wherein the gate conductor polysilicon of the DRAM array first is recessed below the top surface of the silicon substrate. This recessing operation maybe performed using any one of a variety of conventional etching techniques, such as wet etching, chemical dry etching (CDE), plasma etching, and the like. An angled implant of an N-type dopant species then is made through the exposed gate dielectric and into the deep trench sidewall which will contain the gated surface of the vertical MOSFET. This implant forms an N-type doping pocket in the array P-well. At a subsequent processing step, this N-type doping pocket will link up with the outdiffusion from the bitline contact stud, providing an electrical connection between the bitline and the upper source drain diffusion of the vertical MOSFET. It should be noted that this N-type doping pocket is self-aligned with the edge of the gate conductor. As the result of this self-alignment, there essentially are no variations in gate to diffusion overlap capacitance. Following the angled implant of the N-type dopant species, an oxide, optionally, may be grown to reduce the surface state concentration. Then, a chemical vapor deposition (CVD) oxide may be deposited and reactive ion etched (RIE""d), forming spacers on the sidewalls of the apertures above the deep trenches.
An additional layer of an N+ doped polysilicon then is deposited and planarized to the top surface of the high-density plasma (HDP) oxide. Standard processing steps follow that include formation of wordlines, bitline studs (CBs), interlevel dielectrics, and additional wiring levels.
In another embodiment of the present invention, the array gate conductor polysilicon first is recessed below the top surface of the silicon substrate, in the same manner as described above. Then, an arsenic-silicate glass (ASG), or other suitable N-type doped glass, is deposited and reactive-ion etched to form doped glass spacers on the sidewalls of the apertures above the deep trenches. Subsequent hot process steps (for example, junction anneal steps) will cause the dopant from the N-type doped glass to outdiffuse into the silicon of the deep trench sidewall which will contain the gated surface of the vertical MOSFET, then forming N-type bitline diffusion pockets in the array P-well.
As described above in reference to the previous embodiment, an additional layer of N+ doped polysilicon then is deposited and planarized to the top surface of the HDP oxide. Standard, conventional processing then follows, including formation of wordlines, bitline studs, interlevel dielectrics, and additional wiring levels.
The resulting improved vertical MOSFET structure reduces the incidence of shorts between the diffusion stud and the gate conductor, since the structure now contains an additional spacer (in addition to the wordlines spacers) between the bitline diffusion and the gate conductor. Another advantage of the present improved vertical MOSFET structure is the formation of an asymmetric bitline diffusion, such that the bitline diffusion intersects the gated surface of the MOSFET but does not intersect the backside surface of the MOSFET. The asymmetry in the bitline diffusion provides increased electric potential barrier in the parasitic conduction path on the back surface of the MOSFET. Furthermore, since the length of the diffusion is reduced relative to the structures of the prior art, drain induced barrier lowering (DIBL) is reduced as well. Reduced DIBL results in reduced sensitivity of device electrical characteristics to variations in the channel length of the vertical MOSFET (resulting from variations in DT storage node polysilicon recess).
It also should be noted that during the entire processing procedure to form the improved vertical MOSFET structure, as described in both embodiments above, the peripheral support areas of the chip are continuously protected by the top layer of HDP oxide, thus requiring no additional masking techniques during the processing.